Title:
デジタル位相ロックループ
Document Type and Number:
Japanese Patent JP4271582
Kind Code:
B2
Abstract:
The invention relates to a digital phase locked loop (PLL) 12 for demodulating an intermediate frequency signal. The digital phase locked loop12 comprises two coordinate rotation digital computers 24 and 30 in its phase detector. The robustness of the PLL 12 can be improved by means of a gain control circuit 27, a sign detector 20, a carrier monitoring circuit 28 and an adjustable loop filter 32.
Inventors:
Hans-Jürgen, Kuhn
Manfred, Tupuke
Manfred, Tupuke
Application Number:
JP2003566976A
Publication Date:
June 03, 2009
Filing Date:
February 03, 2003
Export Citation:
Assignee:
NXP B.V.
International Classes:
H04L27/06; H03D1/22; H03D3/24; H03L7/085
Domestic Patent References:
| JP6037664A | ||||
| JP2000232493A |
Attorney, Agent or Firm:
Kenji Yoshitake
Hidetoshi Tachibana
Takeshi Sekine
Takahashi
Hidetoshi Tachibana
Takeshi Sekine
Takahashi