PURPOSE: To suppress jitter by forming a closed loop with a control voltage code generating circuit, a D/A converter, a filter and a voltage controlled oscillator so as to control the oscillator with an output of the D/A converter.

CONSTITUTION: A clock CK1 having jitter is frequency-divided into 1/N by a frequency divider 1, and a reset pulse generating circuit 2 generates a reset pulse whose frequency is f0/N. A counter circuit 3 counts number N' of the output clocks CK2 from a voltage controlled oscillator VCO 6 included in a count block being the generated period N.T. A difference between the counted number N' and a setting value N of number of input clocks for a corresponding period is obtained and inputted to a control voltage code generating circuit 7. A closed loop is constituted of the generating circuit 7, a D/A converter 4, a filter 5 and the oscillator 6. Furthermore, the converter 4 converts a coded code NV into an analog signal, the filter 5 eliminates a high frequency component to obtain a control signal Vc of the oscillator 6. Then generated jitter is suppressed.