To obtain a digital PLL circuit which operates stably with respect to variations in noise and source voltage.

This digital PLL circuit comprises a phase comparator 1, which compares the phase of a feedback clock 51 with the phase of a reference signal 50, an up/down counter 2 which counts up or down according to the comparison result of the phase comparator 1, a decoder 3 which decodes the count value of the up/down counter 2, and a numerical control oscillator 4, which has its oscillation frequency controlled according to the decoding result of the decoder 3 and outputs the feedback clock 51, and the numerical control oscillator 4 is constituted by using a ring oscillator composed of an odd number of inverters, which are each provided with a varying means for varying the delay times.