PURPOSE: To realize the digital PLL circuit whose gain is selected depending on the signal quality in which high circuit integration to an LSI is attained.

CONSTITUTION: A phase control circuit 1 adjusts a width of a PLL clock signal so that a PLL clock signal generated from a master clock signal MCK and an EFM signal are synchronously with each other. Speed detection circuits 2, 3 detect a deviation in a speed by counting a pulse width of the EFM signal based on the master clock signal MCK and a phase control circuit 1 changes some pulse widths of the PLL clock signal based on the speed deviation to change an average frequency of the PLL clock signal in proportion to the rotating speed deviation.