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Patent Searching and Data


Title:
DIGITAL PLL CIRCUIT
Document Type and Number:
Japanese Patent JPS6469121
Kind Code:
A
Abstract:

PURPOSE: To eliminate jitter by one clock in the steady-state by constituting the tilted circuit by a D flip-flop and an adder, using the count and controlling the counter after phase comparison.

CONSTITUTION: A part of the counter section consists of D flip-flops 104, 105 and an adder 106. Then a decoder section 107 uses an output of the D flip-flop 103 to output a value being the result of decoding to retard the counter in response to the phase difference to the D flip-flop 105 holding the adder number when the phase of the output signal of the output terminal 108 is led from the phase of the input signal at the input terminal 102 depending on the output of the D flip-flop 103 by one period of the clock given to the clock input terminal 101. Conversely, when it is discriminated that the phase of the output signal at the output terminal 108 is lagged from the phase of the input signal at the input terminal 102, the decoded value is outputted by one period to advance the counter in response to the phase difference to the D flip-flop 105 similarly. Thus, the steady-state jitter by one clock is eliminated.


Inventors:
Nakamoto, Takashi
Application Number:
JP1987000227604
Publication Date:
March 15, 1989
Filing Date:
September 10, 1987
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03L7/06; H04L7/02; H04L7/033; (IPC1-7): H03L7/06; H04L7/02