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Title:
DIGITAL SAMPLE RATE CONVERTING CIRCUIT
Document Type and Number:
Japanese Patent JPS6477331
Kind Code:
A
Abstract:

PURPOSE: To remove adverse influence due to the incompleteness of stuffing by dividing the period of a 1st sampling clock into plural parts, extracting one of the divided parts by a 2nd sampling clock and detecting and computing the time shear of sampling timing.

CONSTITUTION: The period (from t1 to t2) of the sampling timing of the 1st sampling clock is divided into plural (several tens) parts and one of the divided parts is allowed to approximate to the sampling timing t1 of the 2nd sampling clock to find out a factor (k). A control signal generating circuit 231 selects one data out of four input signals on the basis of the factor (k) indicating a phase difference between the 1st sampling clock ck1 254 and the 2nd samplitng clock ck2 255 which is obtained from a factor generating circuit 232. When the factor (k) is 0≤k<b, a latch part 255 is selected, and when a≤k<1 is formed, a latch part 221 is selected. The output signals 262, 263 of selector circuits 229, 230 are selected as data to be used for rectangular interpolation on the basis of the value of the factor (k).


Inventors:
OOTSUKI TOMOMASA
YAMADA MASAHIRO
SAKAMOTO NORIYA
Application Number:
JP23416387A
Publication Date:
March 23, 1989
Filing Date:
September 18, 1987
Export Citation:
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Assignee:
TOSHIBA CORP
TOSHIBA AUDIO VIDEO ENG
International Classes:
H04B14/04; H03H17/00; H03H17/02; H04N7/00; H04N11/04; H04N11/20; (IPC1-7): H03H17/02; H04B14/04; H04N7/00; H04N11/04; H04N11/20
Attorney, Agent or Firm:
Takehiko Suzue (2 outside)