Title:
DIGITAL SERIES INTERFACE WITH DECODED LOGIC
Document Type and Number:
Japanese Patent JPS5863253
Kind Code:
A
Abstract:
A serial data communication system comprises digital send/receive logic 103 and analog send/receive circuitry 104. Data is transmitted over a bus 105, encoded as no pulse for a ONE, alternate positive and negative pulses for successive ZERO's. For transmitting, circuitry 103 includes a timing flip-flop which produces a <3>/<4>-bit-period STROBE signal for each ZERO, and a toggle flip-flop for pulse polarity. For receiving, incoming positive and negative pulses drive separate digital differentiators. A synchronizing counter is controlled to include an extra <> or omit a tick from a normal 16-tick bit period appropriately. A further counter detects a string of at elast 8 ONE's, representing the end of transmission, the data being pre-coded to ensure that such a string of ONE's cannot occur in true transmission of information.
Inventors:
GEERII JIEI GOSU
ROBAATO JII EICHI MOORESU
RANDORU DEII HINRITSUCHISU
TOOMASU OO HORUTEII
ROBAATO JII EICHI MOORESU
RANDORU DEII HINRITSUCHISU
TOOMASU OO HORUTEII
Application Number:
JP16328182A
Publication Date:
April 15, 1983
Filing Date:
September 21, 1982
Export Citation:
Assignee:
HONEYWELL INF SYSTEMS
International Classes:
H03M5/04; G06F13/00; H04L1/00; H04L7/033; H04L25/40; H04L25/49; H04L29/10; (IPC1-7): G06F3/04; H04L13/00; H04L25/00; H04L25/49
Attorney, Agent or Firm:
Koji Hoshino