Title:
DIGITAL SIGNAL DETECTING CIRCUIT
Document Type and Number:
Japanese Patent JP3286025
Kind Code:
B2
Abstract:
PURPOSE: To obtain an accurate digital signal and to accurately reproduce information by reducing interference between code bits of a equalizing signal at the time of A/D conversion and setting to reduce interference code bits of the equalizing signal at the time of binarization.
CONSTITUTION: A reproduced signal generated by a pickup 3 is inputted to waveform equalizer 1, 2. An equalizing characteristic of the equalizer 1 is set so that interference between code bits of a equalizing signal 1a inputted to an A/D converter 4 at the time of A/D conversion is reduced. Further an equalizing characteristic of the equalizer 2 is set so that interference between code bits of a equalizing signal 2a inputted to a binarization circuit 5 at the time of binarization is reduced. Then, in the converter 4, the equalizing signal 1a from the equalizer 1 in which an eye opening rate increases is converted to a digital signal based on a clock signal from a generating circuit almost not including jitter. Thereby, an accurate digital signal can be obtained and information can be accurately reproduced.
Inventors:
Hiroshi Fuji
Application Number:
JP17710293A
Publication Date:
May 27, 2002
Filing Date:
July 16, 1993
Export Citation:
Assignee:
Sharp Corporation
International Classes:
G11B20/10; (IPC1-7): G11B20/10
Domestic Patent References:
| JP3166839A |
Attorney, Agent or Firm:
Kenzo Hara
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