To make the calculation processing of the digital signals of plural channels performable at a high speed based on a prescribed calculation formula.

A register and variables 1-8 are cleared (step S100) and address specification (step S102) for allocating the data of 1CH to an address 1 - the address 9 (horizontal address specification) bit by bit is performed. In the 'CALL NO1' of the step S104, D0 (0-th bit)-D17 (17th bit) are defined depending on what order of the bit of the respective variables the data are substituted in and the data of the respective CH are identified (vertical address specification). They are similarly performed from 2CH to 18CH. Then, in the 'CALL CRC' of the step S116, by parallelly processing the CRC(cyclic redundancy check) calculation of the data of all the channels, calculation time is substantially shortened.