Title:
DIGITAL SIGNAL PROCESSOR CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JPH0675766
Kind Code:
A
Abstract:
PURPOSE: To prevent the program runaway, etc., which are caused by an abnormal sampling cycle when the same arithmetic processing is carried out in each sampling cycle.
CONSTITUTION: A decoder 3 decodes the code of the final step END in an execution program read out of an instruction memory 1. An SR flip-flop 4 which is set by the signal that starts at the failing edge of a sampling cycle is reset. Then the start signal ST entering a program counter 8 is masked by the mask signal SM.
Inventors:
NAKAMOTO TAKASHI
Application Number:
JP12697792A
Publication Date:
March 18, 1994
Filing Date:
May 20, 1992
Export Citation:
Assignee:
NEC CORP
International Classes:
G06F9/30; G06F9/32; G06F9/46; (IPC1-7): G06F9/30; G06F9/32; G06F9/46
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)
Next Patent: PROCESSOR