Title:
DIGITAL SIGNAL PROCESSOR AND DIGITAL SIGNAL PROCESSING METHOD
Document Type and Number:
Japanese Patent JP3912389
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To achieve joining of 1-bit signals produced respectively at different sampling frequencies in an integer multiple relation to each other without causing noise.
SOLUTION: Upon the receipt of a switching request signal 302, a controller 13 controls switching of a changeover switch 15 to provide an output of a switching output signal 305 resulting from smoothly selecting a 64fs rate reproduction signal 300, a 64fs cross fade signal 310 and then a 64fs mute pattern signal 308. When the 64fs mute pattern signal 308 is outputted, the controller 13 generates a switching signal 306 in a properly controlled timing to allow a mute pattern generator 12 to switch the 64fs mute pattern signal 308 into a 128fs mute pattern signal 309. A temporal average of a double integral signal with a minimum repetitive pattern is equal between the mute pattern signals of the two systems.
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Inventors:
Masayoshi Noguchi
Moto Ichimura
Nobukazu Suzuki
Moto Ichimura
Nobukazu Suzuki
Application Number:
JP2004087721A
Publication Date:
May 09, 2007
Filing Date:
March 24, 2004
Export Citation:
Assignee:
ソニー株式会社
International Classes:
G11B20/10; H03M3/02; G10L19/00; G10L21/003; G10L21/04; G11B20/12; H04B14/06; (IPC1-7): H03M3/02; G10L19/00; G10L21/04; G11B20/10; G11B20/12
Domestic Patent References:
| JP3318823B2 | ||||
| JP10051311A | ||||
| JP11328863A | ||||
| JP2000293972A | ||||
| JP2001350497A | ||||
| JP2003017945A |
Attorney, Agent or Firm:
Akira Koike
Eiichi Tamura
Seiji Iga
Eiichi Tamura
Seiji Iga