Title:
DIGITAL SIGNAL PROCESSOR
Document Type and Number:
Japanese Patent JP3117001
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To eliminate noises and discontinuity of data caused by unnecessary data interpolation when data is interpolated to prevent data slip due to the deviation of more than one different sampling frequencies.
SOLUTION: This device has a signal processing circuit 102 which performs mutual conversion processing of two digital data signals and buffers 101 and 103. In such cases, clocks CLK1 and CLK2 are separately inputted to the buffers 101 and 103. The device is further provided with a step-out detector circuit 104 which detects deviation of sampling frequencies based on the clocks CLK1 and CLK2, a jitter detector circuit 105 which detects a jitter amount between both clocks and a data interpolation circuit 106. Thus, the device 20 controls an interpolation data amount based on a jitter amount.
Inventors:
Hideo Sano
Shigeru Ono
Shigeru Ono
Application Number:
JP14669497A
Publication Date:
December 11, 2000
Filing Date:
June 04, 1997
Export Citation:
Assignee:
NEC
International Classes:
H03K19/0175; H04B14/04; H04J4/00; H04L13/08; (IPC1-7): H04B14/04; H03K19/0175; H04L13/08
Attorney, Agent or Firm:
Yosuke Goto (1 person outside)
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