Title:
DIGITAL SIGNAL PROCESSOR
Document Type and Number:
Japanese Patent JP3531208
Kind Code:
B2
Abstract:
PURPOSE: To reduce the silicon size and to reduce the cost of an LSI by reading out immediately the data when both read and write commands are received for a 1st program and then writing the data in a main body storage means after storing them temporarily while a 2nd program is carried out.
CONSTITUTION: Each of data register parts 2-1 and 2-2 receives an instruction to carry out both read and write operations at a time and in a single step and uses a single port RAM to read and write the data to this RAM in mutually different timings. The data are read and written at a time to the part 2-1 in a section 11 where a step OE is outputted. In fact, however, the data are read out of the internal single port RAM at the inside of the part 2-1 and in the section 11 and at the same time the data are temporarily stored in a prescribed latch, and these latched data are written in the single port RAM in the next section 12.
Inventors:
Toda, Hiroyuki
Sekido, Yuichi
Fukui, Mitsuru
Miyamori, Hideo
Sekido, Yuichi
Fukui, Mitsuru
Miyamori, Hideo
Application Number:
JP7276694A
Publication Date:
May 24, 2004
Filing Date:
March 17, 1994
Export Citation:
Assignee:
YAMAHA CORP
International Classes:
G06F12/00; G06F12/06; (IPC1-7): G06F12/00; G06F12/06
Attorney, Agent or Firm:
矢島 保夫
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