PURPOSE: To flexibly and easily configure a high-speed signal processing system by specifying uniquely a computing element action to various operations, combining a function code and a control code corresponding to this and composing a microinstruction code.
CONSTITUTION: The title device has 5-stage structure to which a stage to read data out of a data memory to an instruction executing pipe line stage and input the data to a computing element 106 and a stage to output data from the computing element 106 and write them into the data memory or execute an accumulation or a data rounding by using an accumulator in the computing element are added, a barrel shifter, a multiplier, an arithmetic and logic unit are arranged in the same row in the computing element 106 corresponding to an execution stage in the 5 stages, a barrel shifter for regularizing is connected in the next step corresponding to a writing/accumulation stage and the output of this is made into an input to an adder for rounding/accumulation or the output of the computing element. Thus, a digital signal processing processor whose device configuration is rich in flexibility and simple can be obtained.
UESAWA ISAO
KAMEYAMA MASATOSHI
| JPS5537651A | 1980-03-15 | |||
| JPS5729150A | 1982-02-17 |
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