Title:
DIGITAL SIGNAL RECEIVER
Document Type and Number:
Japanese Patent JP3541722
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a digital signal receiver that reduces a load on the hardware by using a decreased sampling frequency and that decreases the number of times of discrete Fourier transform arithmetic operations made.
SOLUTION: A down-sample section 21 extracts only the even number order samples of real part data Re, where values are in existence in output data Re, Im from a digital orthogonal demodulation section 14. Since the same data are outputted for a 2-sample period, input number of discrete points 4N is halved into 2N. Then a data interpolation section 22, receiving imaginary part data Im outputs an output signal y(n) consisting of data for odd number order sample periods only by shifting the output signal by one sample period, so that values of the data Im exist for odd order number sample periods the same as the case with the real part signal Re (I). Thus, the input number of discrete points 4N of the output signal y(n) is also halved to 2N. Thus, the number of times of arithmetic operations by a discrete Fourier transform(DFT) section 24 can be reduced.
Inventors:
Kazushige Matsui
Application Number:
JP12185399A
Publication Date:
July 14, 2004
Filing Date:
April 28, 1999
Export Citation:
Assignee:
Victor Company of Japan, Ltd.
International Classes:
H04J11/00; H04L27/00; (IPC1-7): H04J11/00; H04L27/00
Attorney, Agent or Firm:
Kaneyuki Matsuura
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