PURPOSE: To generate a signal synchronized with a higher frequency by receiving and controlling an asynchronous signal by two flip flops whose clock inputs are second and third clock signals which have a half frequency of a clock signal to be synchronized with and have opposite phases.

CONSTITUTION: A first clock signal 1 is the target clock with which an asynchronous signal 0 should be synchronized, and a second clock signal 2 has a half frequency of the signal 1. A third clock signal 3 is the inverted signal of the signal 2. A flip flop 11 takes the second clock signal 2 as the clock input and takes the asynchronous signal 0 as the data input and outputs an output signal 4. A flip flop 12 takes the third clock signal 3 as the clock input and takes the asynchronous signal 0 as the data input and outputs an output signal 5. Gates 13 and 14 output AND 6 and OR 7 between output signals 4 and 5 respectively. A selector 15 switches AND 6 and OR 7 to output an objective synchronous signal 8.