PURPOSE: To reduce current consumption by switching a clock frequency in response to the setting mode setting the consecutive photographing or the single photographing.

CONSTITUTION: When the single photographing mode in the photographing mode is selected by an operation panel 11, a CPU 10 switches a changeover switch 9 to the position of fCLK/N. Thus, a low frequency clock is fed to a digital process circuit 5 and a data compression circuit 6 and a high frequency clock is fed to other sections. In this case, when a release switch 12 is depressed, an output signal of a CCD sensor 2 is converted into a digital picture data by an A/D converter section 3 and stored once in a frame memory. Then the processing is applied by the digital process circuit 5 driven by the fCLK/N and the data compression circuit 6. Thus, the digital processing is implemented by 1/N clock to reduce the power consumption per unit time to 1/N.