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Patent Searching and Data


Title:
DIGITAL TRANSMISSION ERROR GENERATOR
Document Type and Number:
Japanese Patent JPS5643848
Kind Code:
A
Abstract:

PURPOSE: To make a quantitative check on whether various digital transmission errors are processed correctly, by generating the digital transmission errors of random polarity and length at a random error generation rate.

CONSTITUTION: Error-generation-rate assigning circuit 8 assigns the generation interval of error data consisting of one bit or a few bits. Error-bit-length counter 9 counts the bit length of one burst error. Error-length assigning circuit 10 assigns the bit length of one burst error. Error-polarity assigning circuit 11 assigns by a switches, etc., one of the holding of transmitted data in a mark, the holding of transmitted data in a space and the inversion of transmitted data.


Inventors:
SHIRAI YOSHITAKE
Application Number:
JP11977279A
Publication Date:
April 22, 1981
Filing Date:
September 18, 1979
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H04L1/00; G06F11/22; G06F13/00; H04L1/24; H04L69/40; (IPC1-7): G06F3/00; G06F11/00; H04L1/00; H04L13/00