To simplify a digital processing circuit by allowing a transmitter to send consecutive video digital data with a code representing a data packet not added thereto and allowing a receiver to detect data of a video horizontal synchronizing signal thereby extracting a packet.

A digital modulation signal such as QPSK sent from a transmitter side is given to a digital demodulator 10, where the signal is demodulated into a serial signal and converted into a parallel signal in the unit of packets at a shift register 11. The shift register 11 provides the output of a parallel signal shifted one by one bit each in the timing of a shift clock generator 18 till a synchronization detector 16 detects a bit pattern of a horizontal synchronizing signal part, and when the synchronization detector 16 detects the bit pattern specific to the horizontal synchronizing signal part, the packet is confirmed and a succeeding serial signal is converted into an N-bit parallel signal and converted into a composite analog video signal by a code converter 12 and a D/A converter 13.