Title:
DIGITAL VIDEO CODING SYSTEM
Document Type and Number:
Japanese Patent JP3373779
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide an addressing control system for a frame difference unit, in which luminance data and chrominance data are simultaneously read to/read from a prediction array and the sequence of write data is maintained the same as an output sequence of transmission data.
SOLUTION: A refinement processor includes a frame difference unit 100 that has a prediction error array (PE array) 1010. The PE array is made up of a common use array that stores luminance data and chrominance data of a macro block of data. The PE array includes a dual port structure and an array read control logic to conduct reading/writing of data with respect to/from the array at the same time. The address selector logic controls addressing of the PE array to maintain synchronization with the writing and reading of the luminance data and chrominance data.
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Inventors:
Jeffrey Dean Carr
Application Number:
JP8325698A
Publication Date:
February 04, 2003
Filing Date:
March 30, 1998
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
G06T9/00; H04N7/32; H03M7/36; H04N7/26; H04N7/50; (IPC1-7): H04N7/32
Domestic Patent References:
| JP7240844A | ||||
| JP6290262A |
Attorney, Agent or Firm:
Hiroshi Sakaguchi (1 person outside)