Title:
DIGITAL VIDEO SIGNAL PROCESSING CIRCUIT
Document Type and Number:
Japanese Patent JPH0248863
Kind Code:
A
Abstract:
PURPOSE:To reduce number of input/output terminals for signal processing by applying parallel/serial conversion to a video signal at an input stage of a semiconductor memory, applying serial/parallel conversion to the signal at an output stage and setting both conversion processing clocks in a specific phase relation. CONSTITUTION:A P/S converter 11 receives a Y signal whose sampling clock is 2fsc, and R-Y and B-Y signals having a frequency of (1/2)fsc in parallel and outputs an 8-bit serial data. A semiconductor memory 12 receives a data output of the P/S converter 11, a control output of a memory control circuit 13 and an address output respectively. An S/P converter 14 receives an 8-bit data output of the semiconductor memory 12 and outputs Y, R-Y and B-Y signals in 8-bit respectively. Moreover, a clock generator 15 gives a prescribed phase relation to the processing clock of the P/S converter 11 and the S/P converter 14 and supplied the result. Thus, number of input/output terminals of the semiconductor memory to convert the digital video signal is saved.
Inventors:
OTSUKA ISAO
Application Number:
JP20050788A
Publication Date:
February 19, 1990
Filing Date:
August 10, 1988
Export Citation:
Assignee:
NEC CORP
International Classes:
G06T1/00; H03K5/135; H03M9/00; H04N5/956; H04N9/64; H04N5/14; (IPC1-7): G06F15/64; H03K5/135; H03M9/00; H04N5/14; H04N5/95; H04N9/64
Attorney, Agent or Firm:
Shin Uchihara
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