Title:
DIGITALLY ADJUSTED TIME DELAY CIRCUIT
Document Type and Number:
Japanese Patent JPH0661773
Kind Code:
A
Abstract:
PURPOSE: To provide a device/method which generates a digitally self-corrected timing delay element by detecting the delay change of the delay element having the controlled delay and controlling the delay against the environmental change. CONSTITUTION: A cascaded detection delay line 20 is formed when the delayed variables 21 and 21' of 1/2Tb are corrected for each delay in a half-bit period. A pair of delay devices 21 and 21' form a bit delay device that delays the time in a 1-bit period. A delay compensator 52 compensates the set-up time of a D flip-flop for a phase detection delay device 50 and a sampling register 70. A post-delay device 60 is used for tracking a pulse when the delay of the delay device is smaller than the nominal value. A control decision circuit 80 analyzes a sampled state code DST71 to decide the time, method, etc., of the control to be applied to an up-down shifter 90 which updates the digital command code of the delay device for the proper delay control.
Inventors:
BIN GUO
JIEEMUSU KIYUBINETSUKU
JIEEMUSU KIYUBINETSUKU
Application Number:
JP14624593A
Publication Date:
March 04, 1994
Filing Date:
June 17, 1993
Export Citation:
Assignee:
ADVANCED MICRO DEVICES INC
International Classes:
H03K5/135; H03H7/30; H03M9/00; H04J3/04; H04J3/06; (IPC1-7): H03H7/30
Attorney, Agent or Firm:
Fukami Hisaro (3 outside)
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