PURPOSE: To provide a direct memory access control circuit which can easily judge which section becomes faulty and a data transfer testing method of this circuit by enabling a CPU to perform direct access between a DPRAM (main storage means) and a DMAC, and the DMAC and a data processing circuit.

CONSTITUTION: Data are transferred between the main storage means 2 and data processing means 4 under the control of a direct memory access controller 3, and, when the data are transferred from the main storage means 2 to the controller 3 and vise versa, and from the controller 3 to the data processing means 4 and vise versa, the transfer data are stored in a 1st storage means or 2nd storage means under the control of 1st and 2nd control means, and an arithmetic processing means 1 judges that the transfer is correctly performed when the stored data and transfer data are identical.