PURPOSE: To reduce the load of a host processor by providing an address FIFO and a size FIFO buffers to simultaneously store plural memory areas to be the objects of access.

CONSTITUTION: A host processor 1 sets start addresses and area sizes for memory areas A8, B9 and C10 respectively to an address FIFO buffer 6 and a size FIFO buffer 7 in the order of transfer and afterwards, the activation of a DMA transfer is requested to a DMA controller 5. Next, in the controller 5, the data of the area A8 are read out from the buffers 6 and 7 and the data transfer of the area A8 is started by DMA. In the controller 5, after the end of the DMA transfer of the data in the area A8 is detected, further, the data of the area B9 are read out from the buffers 6 and 7 and the DMA transfer is started. When the DMA transfer of the area B9 is finished, finally, the DMA transfer of the data in the area C10 is similarly executed.