To unnecessitate stand-by for a long time by providing a DMA arbitration device arbitrating a memory using right and a DMA engine controller generating a memory control signal.

At the time of separating a DMA transmission cycle to data transmission (a first cycle) from a source memory to a DMA data buffer 170 and data transmission (a second cycle) from the DMA data buffer 170 to a destination memory and setting each cycle to be basic DMA cycle, the DMA arbitration device 130 receives an access request from at least one master using a source memory or the destination memory in the middle of transmitting DMA to arbitrate the memory using right by the unit of a basic DMA transmission cycle. Then the DMA engine controller 140 requests the memory using right to the DMA arbitration device 130 to generate the memory control signal necessary for DMA transmission and a memory control signal necessitated by a master with the memory using right and to generate information on the number of DMA transmission times at a DMA count register 100.