PURPOSE: To obtain a DMA controller which has a latent capability for error recovery and can get out from an error state elegantly when the error state is detected by providing an error circuit which makes a DMA controller execute a completed task before DMA transfer is completed.
CONSTITUTION: An error detecting circuit 115 monitors information from a direct memory access(DMA) control backup circuit 110 and a DMA control state machine 120 and generates a DMA error signal DMA-ABORT if an error state is detected during DMA transfer. A port-90 control circuit 506 of a central arbitration control point circuit sets a TIMEOUT signal to an active state. The TIMEOUT signal is supplied to the DMA control state machine 120 and a bus interface unit, and an ERROR state is entered. In the ERROR state, a given completed task is executed before an IDLE state is entered.
BEECHIYAARA FUOUADO BOURII
SHIYAAUTSUDO BURANON
RICHIYAADO JIERAADO HOFUMAN
TERENSU JIYOOZEFU ROOMAN
