PURPOSE: To attain DMA transfer without reducing the using efficiency of a processor by separating buses at the time of DMA transfer.

CONSTITUTION: When a DMA request is outputted from an I/O apparatus 5 to a DMA control circuit 2, the circuit 2 makes the outputs of bus buffers floating status. Namely, an address bus 11b, a data bus 12b and control buses 13b, 14b are separated from an address bus 11a, a data bus 12a and control buses 13a, 14a. Therefore, the right of possession of the address bus 11a, the data bus 12a and the control buses 13a, 14a is assigned to a microprocessor 1, but that of the address bus 11b, the data bus 12b and the control buses 13b, 14b is transferred to the DMA control circuit 2.