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Patent Searching and Data


Title:
DISCONNECTION ID ALLOCATING SYSTEM OF STO STACK
Document Type and Number:
Japanese Patent JPS5942684
Kind Code:
A
Abstract:

PURPOSE: To access two virtual address spaces even when an STO stack is disconnected, by allocating ID for STO disconnection forcibly in accordance with contents of head addresses of a segment table set to two control registers when the STO stack is disconnected due to a fault or the like.

CONSTITUTION: When an STO stack 4 is disconnected and a disable signal goes to logic "1", disconnection ID allocating circuits 9 and 10 send disconnection ID, which is different from ID set to the first and the second ID registers 7 and 8, to an out-pointer 11. This disconnection ID is controlled in accordance with the output of a comparing circuit 1. Disconnection ID used for disconnection of the STO stack 4 is not registered in a table TBL. Consequently, two spaces beginning with head addresses of the segment table set to control registers CR1 and CR2 are accessed without hindrance.


Inventors:
OOYA MASAYUKI
IYOTA HIDEO
Application Number:
JP15149582A
Publication Date:
March 09, 1984
Filing Date:
August 31, 1982
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F12/10; G06F12/08; (IPC1-7): G06F13/00
Attorney, Agent or Firm:
Kyotani Shiro