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Title:
DISCRETE FOURIER-TRANSFORM CIRCUIT WITH SWITCHED CAPACITOR
Document Type and Number:
Japanese Patent JPS63121311
Kind Code:
A
Abstract:

PURPOSE: To simutaneously obtain all the Fourier-transform outputs and to output them as sine waves corresponding to the degrees of basic frequency with a simple constitution by connecting plural delay means with switched capacitors in a cascade and connecting coefficient multiplication means with the switched capacitors between an input edge and the respective delay means.

CONSTITUTION: The plural SC delay circuits 11, 12∼1n are connected to the input edge 10 to which input signals are given. The circuits 11, 12∼1n sequentially delay the input signals and output the signals corresponding to a specified time series. And the SC coefficient multiplication circuit 20 is connected to the input edge 10 and the SC coefficient multiplication circuits 21, 22∼2n are connected to the outputs of the respective circuits 11, 12∼1n. Now, a constant is set, which is obtained when the circuits 11, 12∼1n sequentially delay the input signals to the circuits 20, 21, 22∼2n. The outputs from the respective circuits 20, 21, 22∼2n are added in an addition circuit 5 and then the signals corresponding to the basic frequency are outputted as the form of sine wave with a simple constitution of the circuit.


Inventors:
YONEDA MASAJIRO
NAKANISHI ISAO
SASAKI ITSUO
KANEHIRA AKIRA
KASAI TAMOTSU
Application Number:
JP26805386A
Publication Date:
May 25, 1988
Filing Date:
November 11, 1986
Export Citation:
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Assignee:
YONEDA MASAJIRO
International Classes:
H03H19/00; G06G7/19; (IPC1-7): G06G7/19; H03H19/00
Domestic Patent References:
JPS6028319A1985-02-13
JPS52109354A1977-09-13
Attorney, Agent or Firm:
Fukami Hisaro



 
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