To solve the problems of a conventional display control semiconductor integrated circuit with a single-port RAM built in that the load of a CPU control system is increased, and the cycle time of transferring display data via the RAM is prolonged.

This display control semiconductor integrated circuit 101 causes an internal synchronous control circuit 5 provided therein to control via a built-in single-port RAM 4 the transfer of display data between a CPU 2 and a display panel 3. This control of the display data transfer is effected in such a way that when a write access is made to the RAM 4 from the CPU 2 or a read access (write/read) is made to the CPU 2 from the RAM 4 to make a read access (display read) to the display panel 3 from the RAM 4 for the display data, write/read instructions are always given precedence over display read instructions without the need to output a ready signal to the CPU 2, regardless of whether or not the write/read instructions conflict with the display read instructions.