PURPOSE: To develop a hatching pattern or the like at high speed by effectively utilizing a BiTBLT system without any load to a CPU and to surely develop the pattern in an arbitrarily designated area only by adding a simple circuit without changing the BiTBLT system.

CONSTITUTION: A BiTBLT sequence controller 1 successively updates the source address of the transfer destination and the destination address of the transfer destination. When a hatching mode is set to a mode set register 18, a NAND gate 19 inhibits an increment signal XINC from the controller 1, the increment operation of an X counter 13 on the source side is stopped and an AND gate 20 and a 32-multiple detection circuit 21 or the like load/increment a Y counter 12 on the source side in a prescribed cycle so as to develop the block pattern of the transfer source to the transfer destination while repeating it several times.