To reduce the power consumption of a display device which uses a time gradation system when a multi-gradation display is not necessary.
In a 2nd display mode wherein the number of gradations is reduced to two as compared with a 1st multi-gradation display mode, a memory controller of a signal control circuit that the display device has eliminates writing of a digital video signal of the low-order bits to a memory. Further, a read of a digital video signal of low-order bits from the memory is eliminated. The amount of information of a digital video signal inputted to a source signal line driving circuit is reduced. In response to the operation, a display controller sets a display period wherein a display is made long. Thus, the number of gradations is decreased to make a frame period longer than that of the 1st display mode.
JPH02304593 | MULTIPICTURE DISPLAY DEVICE |
JP2002351377 | IMAGE DISPLAY METHOD AND IMAGE DISPLAY DEVICE |
JPH11133921A | 1999-05-21 | |||
JP2001343933A | 2001-12-14 | |||
JP2002149119A | 2002-05-24 |
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