To provide a display device in which an MIS transistor whose semiconductor layer is an amorphous semiconductor and an MIS transistor whose semiconductor layer is a polycrystalline semiconductor are formed, wherein crystallinity of the semiconductor layer comprising the polycrystalline semiconductor is improved when each of MIS transistors is structured as a bottom gate.
The display device includes a first MIS transistor formed on a first region of a substrate and a second MIS transistor formed on a second region different from the first region, each of which has a gate electrode between the substrate and semiconductor layer. The first MIS transistor has a semiconductor layer comprising an amorphous semiconductor, while the second MIS transistor has a semiconductor layer comprising a polycrystalline semiconductor. The gate electrode on the second MIS transistor is smaller in thickness than that on the first MIS transistor.
KAMO NAOHIRO
NIIMOTO HIDEAKI
