To provide a semiconductor circuit operating correctly as a shift register without a level shifter while reducing the number of transistors included in the circuit.

A display device includes m stages (m is an arbitrary positive integer satisfying m≥3) of inverter circuits and circuit groups each including a p-channel transistor with a first terminal connected to a high-potential power supply and an n-channel transistor with a first terminal connected to a low-potential power supply. A clock signal is input to a gate of the n-channel transistor of the circuit group of the (2n-1)-th stage (n is an arbitrary integer satisfying m≥2n≥2). An inversion clock signal is input to the gate of the n-channel transistor of the circuit group of the 2n-th stage (n is an arbitrary integer satisfying m≥2n≥2).