Title:
表示装置
Document Type and Number:
Japanese Patent JP5013697
Kind Code:
B2
Abstract:
A capacitance setting line is disposed at the top end of a pixel, a light emission setting line is disposed at the bottom end of the pixel, and a gate line is disposed at the center between both the lines. A selection transistor, a potential control transistor and a capacitor are disposed between the gate line and a capacitance setting line. A short-circuit transistor, a drive transistor and a drive control transistor are disposed between the gate line and the light emission setting line. With such an arrangement, the efficient arrangement of wiring contacts can be performed, and an aperture ratio can be increased.
Inventors:
Shoichiro Matsumoto
Kanehara Yasunori
Kanehara Yasunori
Application Number:
JP2005304911A
Publication Date:
August 29, 2012
Filing Date:
October 19, 2005
Export Citation:
Assignee:
Sanyo Electric Co., Ltd.
International Classes:
G09F9/30; G09G3/20; G09G3/30; H01L27/32; H01L51/50; H05B44/00
Domestic Patent References:
| JP2004004348A | ||||
| JP2005157308A | ||||
| JP2003223138A | ||||
| JP2005326828A |
Foreign References:
| WO2003027997A1 |
Attorney, Agent or Firm:
Kenji Yoshida
Jun Ishida
Jun Ishida