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Title:
DISPLAY DRIVING SYSTEM FOR ELECTRONIC APPARATUS INCLUDING DISPLAY UNIT
Document Type and Number:
Japanese Patent JPS5567835
Kind Code:
A
Abstract:

PURPOSE: To decrease both the signal lines of the electronic apparatus including the display unit and the output terminals of the arithmetic control unit by using the digit driving signal transmission line of the display unit in common to the address signal line of the external memory.

CONSTITUTION: Timer 14 within arithmetic control information (CPU)10 delivers the signals for the 1st time band to transmit the address information and the 2nd time band showing the interruption period via address bus AB. The addresses of address buses ABOW11 memorize the contents of data bus DB as the address designation of external memory 4 or reads out the contents to DB from the memory at the 1st time band. At the interruption time band, digit driving signals T0W11 of display unit 20 corresponding to the digit designated by the numerical value of digit counter CT of CPU10 are supplied from bus AB, and the contents to be displayed at the digit are supplied to the display data transmission line SB via RAM13 from keyboard 30. Thus the contents of the full digits are displayed in sequence.


Inventors:
SAKAGUCHI SHIYUNICHI
Application Number:
JP14017378A
Publication Date:
May 22, 1980
Filing Date:
November 14, 1978
Export Citation:
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Assignee:
OMRON TATEISI ELECTRONICS CO
International Classes:
H03M11/20; G06F3/02; G06F3/023; G06F3/147; (IPC1-7): G06F3/02; G06F3/147