PURPOSE: To obtain a circuit of simple, inexpensive constitution, by providing a shift register which holds a display input signal for a prescribed time under switching control over a short-period clock signal and a long-period clock signal.
CONSTITUTION: When a shift register SR9 is reset, a short-period clock signal 5 for chattering removal is supplied invariably to the clock input terminal CK of the SR9 through an AND circuit 17 and an OR circuit 18. When a display input signal 1 goes up to 1, the SR9 is set, a data input terminal DI is held at 1, and the signal 5 is inputted successively to store numbers of 1 in the SR9 successively. When this state continues for longer than 50ms, the output terminal Q1 of the SR9 is held at 1 and even if the signal 1 goes down to 0, it is not reset and closes the circuit 17, stopping the inputting of the signal 5. Eevry time when a long-period display transmission timing signal 3 for 1∼6sec period is supplied, the SR9 is driven slowly and after the transmission is repeated more than once, the terminal Q2 is held at 1 to input the signal 5 to the terminal CK of the SR9. Then when numbers of 0 of the signal 1 succeed for longer than 50ms, the SR9 is reset to an initial state.
| JPH05145675 | REMOTE SIGNAL DETECTION SYSTEM |
| JPH05145540 | VITERBIRECEIVER HAVING IMPROVED TIMING MEANS |
ARAKI JIYUNICHI
NAKANO FUMIO
