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Patent Searching and Data


Title:
DISPLAY METHOD FOR DEFECT
Document Type and Number:
Japanese Patent JPS5788352
Kind Code:
A
Abstract:

PURPOSE: To prevent the false detection of defects at the inspection of the 2nd time by putting on defect marks at the 2nd time in the case of comparing and inspecting the same circuit patterns twice.

CONSTITUTION: A printed substrate 1 having three circuit patterns (1), (2), (3) is mounted in an XY stage 3. Pattern detectors A, B are disposed spacially at a predetermined distance, and irradiation beams 7, 7' are reflected respectively downward by semitransparent mirros 6, 6', and arrive at the substrate 1. The beams reflected from the circuit patterns pass through the mirrors 6, 6', are condensed by lenses 5, 5', and arrive respectively at pattern detectors A, B, by which they are converted to electric signals and these signals are fed to a comparing decision circuit 4, by which the patterns are compared. The range of inspecting the circuit patterns double is determined by the coordinate signal from a coordinate detector 12 as well as the number of patterns and a pattern pitch signal x. If there is any defect in the circuit patterns within this range, marking with a marker 8' is carried out.


Inventors:
HARA YASUHIKO
UTO YUKIO
Application Number:
JP16459080A
Publication Date:
June 02, 1982
Filing Date:
November 25, 1980
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L21/66; G01N21/956; G03F1/84; H01L21/027; (IPC1-7): G01N21/88; H01L21/30