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Title:
DISPLAY PROCESSOR
Document Type and Number:
Japanese Patent JPH09330201
Kind Code:
A
Abstract:

To improve a display processing performance by providing a bus control means with a mapping state holding means which holds a copy of the contents held by a state holding means and shorten the time of response to a CPU and the time of window switching.

The bus control means 2 is equipped with address holding means 12 and 13 and mapping state holding means 14 and 15. Through a timer means 16, the bus control means 2 reads the contents of state holding means 18 and 19 out to a bus 7 according to the address holding means 12 and 13 and periodically updates the contents of the mapping state holding means 14 and 15. A mapping display storage means 17 in the bus control means 2 temporarily stores part of contents of image display storage means 5 and 6. The mapping display storage means 17 servers as a buffer and when data stored in the image display storage means 5 and 6 are needed, access to the image display storage means may be only started through a drawing means 3 in parallel to data processing of part of the data stored in the mapping display storage means 17, thereby making the processing fast on the whole.


Inventors:
NAKAMURA HIROSHI
Application Number:
JP15262196A
Publication Date:
December 22, 1997
Filing Date:
June 13, 1996
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F3/14; G06F3/048; G06F3/0481; G06F3/153; G09G5/00; G09G5/14; G09G5/36; G09G5/39; (IPC1-7): G06F3/14; G09G5/00; G09G5/14; G09G5/36
Attorney, Agent or Firm:
井桁 貞一



 
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