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Title:
DISTORTION ELIMINATION CIRCUIT, DISTORTION COMPENSATION AMPLIFYING APPARATUS AND ITS OPERATION CONTROL METHOD
Document Type and Number:
Japanese Patent JP2004320651
Kind Code:
A
Abstract:

To provide a distortion compensation amplifying apparatus capable of eliminating a distortion component regardless of whether a frequency band of an input signal is wide or narrow.

A synthetic signal of an input signal that is amplified by a main amplifier 2 and then delayed by a DL4, and an output signal of a sub amplifier 8 is extracted by a CDC10 and separated into two signals of mutually different frequencies cooperatively covering a frequency band to be used by BPF 21, 22, synchronism of the separated signals is detected by the output signal of the sub amplifier 8 or its orthogonal signal (a signal with a phase difference of 90°) extracted by the CDC20 by synchronism detection circuits 23, 24, and the synchronism detected signal is converted into a control signal and inputted to a control part of the sub amplifier 8 by a signal processing circuit 25, thereby rightly canceled the distortion component contained in the output signal of the main amplifier 2 in a composition part 9.


Inventors:
OGAWA KAZUYOSHI
OZAWA TOSHIO
Application Number:
JP2003114842A
Publication Date:
November 11, 2004
Filing Date:
April 18, 2003
Export Citation:
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Assignee:
SHIMADA PHYSICAL CHEM IND CO
International Classes:
H03F1/32; (IPC1-7): H03F1/32
Attorney, Agent or Firm:
Masatake Suzuki