PURPOSE: To provide a very high-speed retiming reproducing circuit whose maximum operation speed is higher than heretofore.

CONSTITUTION: A unit circuit is constituted of a 1st series transistor(TR) group Q11 and Q14 and a 2nd series TR group Q21 to Q24 in which two TRs are connected in cascade to each other. A 1st data signal is inputted to one terminal of a 1st transmission line X1 and a 2nd data signal with a prescribed time difference from the 1st data signal is inputted to one terminal of a 3rd transmission line X3. In addition, a 1st clock signal is inputted to one terminal of a 2nd transmission line X2 and a 2nd clock signal inverted from the 1st clock signal is inputted to one terminal of a 4th transmission line X4. One terminal of a 5th transmission line X5 is used as an output terminal Dout for a retiming- reproduced data signal.