To provide a divider circuit which is suitable to divide a reference clock into the one-over-integer value that is not equal to the n-th power of 2 by feeding the output of a logical gate that provides AND between this output and a reset signal back to a data input terminal and outputting the clock obtained by dividing the reference clock into the specific value from an output terminal.

A 2-divider DVD1 divides a reference clock CK into two clocks by feeding the output of an inverter INV5 back to the data input terminal of a flip-flop F/F-5. In other words, the clock CK is once divided into 1/2 by the divider DVD1 and then into 1/n and outputted so that (n-1) pieces of flip- flops and the logical gates are alternately arranged and cascaded together and also the output of a multi-input logical gate using the outputs of those logical gates and a reset signal as inputs is fed back to the input terminal of the F/F-5.