Title:
DIVIDER CIRCUIT
Document Type and Number:
Japanese Patent JP2016122897
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a divider circuit capable of achieving stability of a division operation by suppressing fluctuations in a self oscillation frequency of a flip-flop circuit due to variations in manufacturing transistors for sample or fluctuations in environmental temperatures.SOLUTION: A gm constant bias circuit 16 is configured to control a bias voltage Vb applied to transistors 15a-15d for current mirror and suppress fluctuations in a self oscillation frequency fof a flip-flop circuit 3. This configuration can suppress fluctuations in the self oscillation frequency fof the flip-flop circuit 3 due to variations in manufacturing transistors 13a-13d for sample or fluctuations in environmental temperatures.SELECTED DRAWING: Figure 1
Inventors:
HAGIWARA TATSUYA
TANIGUCHI EIJI
TANIGUCHI EIJI
Application Number:
JP2014260535A
Publication Date:
July 07, 2016
Filing Date:
December 24, 2014
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H03K23/00; H03K3/3562; H03L7/08
Domestic Patent References:
| JP2011124854A | 2011-06-23 | |||
| JP2004523830A | 2004-08-05 | |||
| JP2014222867A | 2014-11-27 |
Foreign References:
| WO2012131795A1 | 2012-10-04 |
Other References:
DAEIK D.KIM: "A 94GHz Locking Hysteresis-Assisted and Tunable CML Static Divider in 65nm SOI CMOS", SOLID-STATE CIRCUITS CONFERENCE, 2008. ISSCC 2008. DIGEST OF TECHNICAL PAPERS. IEEE INTERNATIONAL, JPN6017038422, 3 February 2008 (2008-02-03), pages pp.460, 461, 628
Attorney, Agent or Firm:
Hideaki Tazawa
Hamada Hatsune
Nakashima Shigeru
Hideo Kawamura
Tatsuya Sakamoto
Tsujioka Masaaki
Hamada Hatsune
Nakashima Shigeru
Hideo Kawamura
Tatsuya Sakamoto
Tsujioka Masaaki
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