Title:
分周回路
Document Type and Number:
Japanese Patent JP5097573
Kind Code:
B2
Abstract:
Disclosed is a frequency divider including first to fifth FFs(flip-flops), each of which receives a common clock signal and samples and outputs an input signal responsive to an effective edge of the clock, an output signal of the 1st FF being supplied to the 2nd FF, a first logic gate which receives an output signal of the 2nd FF and a first control signal and outputs the output signal of the 2nd FF, when the first control signal is of a first value, and outputs a predetermined value, when the first control signal is of a second value, the output signal of the first logic gate being supplied to an input of the 3rd FF; a second logic gate which receives an output signal of the 1st FF and a second control signal and outputs an output signal of the 1st FF, when the second control signal is of the first value and outputs the predetermined value, when the second control signal is of the second value, the output signal of the second logic gate being supplied to the 4th FF; and a third logic gate which receives an output signal of the 3rd FF and an output signal of the 4th FF and outputs an output signal of a first value, when both inputs thereof are of a second value, the output signal of the third logic gate being supplied to an input of the 5th FF, an output signal of the 5th FF being fed back to an input of the 1st FF.
Inventors:
Masashi Mitsuishi
Application Number:
JP2008043132A
Publication Date:
December 12, 2012
Filing Date:
February 25, 2008
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H03K23/64
Domestic Patent References:
| JP2001186012A | ||||
| JP1198009A | ||||
| JP1221019A | ||||
| JP60216629A |
Attorney, Agent or Firm:
Kato Asamichi