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Title:
分周器及び分周方法
Document Type and Number:
Japanese Patent JP5005821
Kind Code:
B2
Abstract:
A frequency divider comprises a cascade of at least two triggered delay elements (FF1, FF2, ...), a reference frequency input (FIN) and a clock output (FOUT). The triggered delay elements (FF1, FF2) are configured to forward a state of an input signal at a respective data input (D1, D2) to a respective data output (Q1, Q2) either for a rising clock edge of a clock signal at a respective clock input (C1, C2) or for a falling clock edge of the clock signal, depending on a control signal at a respective trigger control input (PH1, PH2). Clock inputs (C1, C2) of the delay elements (FF1, FF2) are coupled to the reference frequency input (FIN). The data input (D1) and the trigger control input (PH1) of the first delay element (FF1) of the cascade are coupled to the data output (Q2, QN) of the last delay element (FF2, FFN) of the cascade. The data input (D2, ...) and the trigger control input (PH2, ...) of further delay elements (FF2, ...) of the cascade are coupled to the data output (Q1, ...) of a respective preceding delay element (FF1, ...) of the cascade. The clock output (FOUT) is coupled to the data output (Q2, ...) of the last delay element (FF2, ...) of the cascade. Hereby the trigger control input (PH1, ...) of one of the delay elements (FF1, ...) of the cascade is coupled to the corresponding data output (QN, ...) by inverting means (INV1, ...) and the respective data inputs (D2, ...) of the other delay elements (FF2, ...) of the cascade are coupled to the corresponding data output (Q1, ...) by respective inverting means (INV2, ...).

Inventors:
Ruggero Leon Cavallo
Application Number:
JP2010529334A
Publication Date:
August 22, 2012
Filing Date:
October 01, 2008
Export Citation:
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Assignee:
Austria Microsystems AG
International Classes:
H03K23/64; H03K21/00
Domestic Patent References:
JP2007221587A
JP5191272A
JP4115623A
JP63283316A
JP5259895A
JP5534572A
Attorney, Agent or Firm:
Seiryu Corporation



 
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