Title:
選択可能な周波数及びデューティサイクルを有する分周器
Document Type and Number:
Japanese Patent JP6831922
Kind Code:
B2
Abstract:
A frequency divider system and method includes a split-divisor frequency divider module. The split-divisor frequency divider module receives a clock signal and generates an output signal based on a first divisor and a second divisor. The clock signal and output signal each have rectangular waveforms characterized by a respective frequency and pulse width. The frequency of the output signal is a selectable integer fraction of the frequency of the clock signal, the frequency of the output signal being selected based on a sum of the first and second divisors. The pulse width of the output signal is a selectable integer number of clock cycles, the pulse width of the output signal being selected based on at least one of the first divisor and the second divisor.
Inventors:
Richard Richards
Application Number:
JP2019545879A
Publication Date:
February 17, 2021
Filing Date:
September 26, 2017
Export Citation:
Assignee:
Integrated Device Technology Incorporated
International Classes:
H03K23/64
Domestic Patent References:
| JP2007221587A | ||||
| JP2015119504A | ||||
| JP2014090381A | ||||
| JP2001292058A |
Foreign References:
| US8378719 | ||||
| US20140003570 |
Attorney, Agent or Firm:
Hiraki International Patent Office