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Patent Searching and Data


Title:
分周装置
Document Type and Number:
Japanese Patent JP3571228
Kind Code:
B2
Abstract:
The frequency divider includes a frequency divider element (H) which forms a first intermediate signal (1) with half the frequency (f) of an input signal (IN). An intermediate divider (4/5) produces a second intermediate signal (2) with a frequency of one eighth of the input signal, or of one tenth of the input signal, by dividing the first intermediate signal through four or five, respectively, in response to a switching signal (U). A divider expansion (EXT) is equipped with 2<(N-2)> divider stages (FF5... FF8), in which its next to the last divider stage (FF7) produces an output signal (OUT) with a frequency of f/N and/or f/(N+1). A combination circuit (A3) produces the switching signal from a control signal (MOD) and output signals (3... 6) of the divider expansion.

Inventors:
Herbert Knap
Wilhelm Wilhelm
Application Number:
JP26493698A
Publication Date:
September 29, 2004
Filing Date:
September 18, 1998
Export Citation:
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Assignee:
Siemens Aktiengesellschaft
International Classes:
H03K23/00; H03K23/58; H03K23/66; (IPC1-7): H03K23/00
Domestic Patent References:
JP4068919A
Other References:
Craninckx, J. & Steyaert,A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in0.7-μm CMOS,IEEE Journal of Solid-State Circuits,米国,IEEE,1996年 7月,Volume 31, Issue 7,page 890-897
Kasahara, J. et.al.,10GHz GaAs JFET dual-modulus prescalar IC,Electronics Letters,米国,IEEE,1989年 7月,Volume 25, Issue 14,page 889-890
Attorney, Agent or Firm:
Toshio Yano
Toshiomi Yamazaki
Takuya Kuno
Reinhard Einsel