Title:
DMA CONTROLLER FOR COMMUNICATION
Document Type and Number:
Japanese Patent JP3186247
Kind Code:
B2
Abstract:
PURPOSE: To reduce the load of a CPU at the time of executing the DMA transfer of received serial data to a memory.
CONSTITUTION: When the 3rd data counted from the head of serial data indicate the number of continuously sent serial data, a CPU sets up '3' in a counter circuit 104 to activate a counter control signal line 116. Thereby when the 3rd serial data are received by a reception shifting register 102, a receiving data write control line 114 is activated. When the counting result of active signals in the circuit 104 coincides with the set value '3' based upon the 3rd active signal, a write control signal line 115 is activated. When the signal line 115 is activated, the 3rd serial data outputted from the circuit 102 are stored in a DMA transfer frequency register 103 to allow DMA transfer control circuit to start DMA transfer.
Inventors:
Kazuya Yonezu
Application Number:
JP25590292A
Publication Date:
July 11, 2001
Filing Date:
August 31, 1992
Export Citation:
Assignee:
NEC
International Classes:
G06F13/00; G06F13/28; G06F13/38; (IPC1-7): G06F13/28
Domestic Patent References:
| JP470947A | ||||
| JP4169955A | ||||
| JP57174737A |
Attorney, Agent or Firm:
Naka Kanno
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