PURPOSE: To obtain a general-purpose DMA controller which works at a high speed by using an arithmetic circuit to count all at once the value equivalent to the byte number of data width.

CONSTITUTION: The address, the device range value and the bus range value are supplied with shift as an address range input 10 with a bus clock 13 and a device clock 14 and set at an address register RG3, a device range counter 2 and a bus range register RG1, respectively. Then the data width 15 is designated from the outside for the data to be transferred. Then an operator 6 performs an addition of addresses held at the RG3 as well as a subtraction of the data number of the RG1 by an amount equivalent to the byte number of the width 15 for every supply of the clock 13 when the data transfer is started. An encoder 5 produces an effective byte position and delivers it as an effective data position display 12. This display has an OR with the display output of an effective data position produced within the encoder 5 and is delivered since the effective data position is changed during the data transfer by an effective data position input 16.