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Title:
DMA TRANSFER CONTROLLER
Document Type and Number:
Japanese Patent JPH09231162
Kind Code:
A
Abstract:

To always execute equal transfer by updating priority only when the output of a selection circuit is equal to the output of an intra-word counter.

A channel priority management part 7-2 compares the output of the intra-word transfer number count part 7-5 whose one bus access termination is not informed by a bus access control part 7-1 with the initial value of a transfer counter, which is obtained by a bus width comparison part 7-5-1. When they are equal, the channel number of the highest priority is selected among the plural channels requesting transfer. The bus width comparison part 7-5-1 compares the number of count up bytes among the channels, and obtains the number of the bytes of L.C.M. The respective intra-word transfer counters 7-5-2 and the channel priority control part 7-2 are informed so that a value obtained by reducing only one from the number of the bytes of L.C.M is set to be the initial value of the intra-word transfer number counter 7-5-2.


Inventors:
OKABE KAZUYA
Application Number:
JP3619596A
Publication Date:
September 05, 1997
Filing Date:
February 23, 1996
Export Citation:
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Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
G06F13/28; G06F13/30; (IPC1-7): G06F13/30; G06F13/28
Attorney, Agent or Firm:
Toshiaki Suzuki



 
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